1. Field of the Invention
The present invention relates to a Non-Volatile Dynamic Random Access Memory (hereinafter referred to as "NVDRAM") in which a Dynamic Random Access Memory (hereinafter referred to as "DRAM") and an Electrically Erasable Programmable Read-Only Memory (hereinafter referred to as "EEPROM") are used in combination, and to an NVDRAM in which a ferroelectric material is used.
2. Description of the Related Art
Conventional NVDRAMs may be categorized into two types. One is NVDRAMs in which a DRAM, which is a volatile semiconductor memory device, and an EEPROM, which is a non-volatile semiconductor memory device, are used in combination (hereinafter, this type of NVDRAM will be referred to as a "DRAM/EEPROM type NVDRAM"). The other is NVDRAMs in which memory cells composed of a ferroelectric material are used so as to function both as volatile memory devices and as non-volatile memory devices (hereinafter, this type of NVDRAM will be referred to as a "ferroelectric type NVDRAM").
A detailed description of DRAM/EEPROM type NVDRAMs can be found in "A 256k-bit Non-Volatile PSRAM with Page Recall and Chip Store", 1991 Sym. VLSI circuit Dig. Tech. papers, May, pp. 91-92. This NVDRAM operates in a DRAM-mode and a store-mode. Specifically, during usual operations, a DRAM including volatile memory cells is accessed in a DRAM-mode. On the other hand, immediately before the NVDRAM is turned off, the data stored in the DRAM is saved in an EEPROM including non-volatile memory cells. As a result, high-speed accesses to the volatile DRAM can be realized during usual operations, while allowing the data stored in the DRAM to be stored in the EEPROM before the NVDRAM is turned off, so as to be retained therein. The data stored in the non-volatile EEPROM can be read back into the DRAM in a recall-mode.
A description of a ferroelectric type NVDRAM can be found in the following documents: (1) "An Experimental 512-bit Non-Volatile Memory with Ferroelectric Storage Cell" IEEE Journal of Solid State Circuits, vol. 23, pp. 1171-1175, October, 1988; and (2) "A Ferroelectric DRAM cell for High-Density NVDRAM's", IEEE Electron Device Lett., vol. 11, pp. 454-456, October, 1990.
The above-mentioned ferroelectric type NVDRAM includes memory cells each incorporating a capacitor element in which a ferroelectric material thin film having a perovskite type crystal structure, e.g. Y1, (a newly developed ferroelectric ceramic having a relatively small deterioration due to rewriting commonly referred to by the same name; the composition thereof is yet to be published), PZT (PbZrTiO.sub.3, or lead zirconate titanate), PLZT (PbLaZrTiO.sub.3), PbTiO.sub.3, etc. is interposed.
When an a.c. current is applied to the above-mentioned capacitor element, the polarization state of the ferroelectric material interposed in the capacitor element shows hysteresis characteristics shown in FIG. 1. As seen from FIG. 1, the polarization state of the ferroelectric material, which is at point A when it is not polarized, shifts to point B when a positive electric field is applied to the ferroelectric material. The polarization state of the ferroelectric material returns only to point C (instead of A) when the electric field is removed, thus resulting in a positive remanent polarization. This remanent polarization vanishes when a negative anti-electric field is applied. By further increasing the intensity of the negative electric field, the polarization state of the ferroelectric material is inverted so as to shift to point D. The polarization state of the ferroelectric material returns only to point E when the electric field is again removed, thus resulting in a negative remanent polarization.
Thus, by allowing the polarization state of the ferroelectric material to be inverted so as to achieve positive or negative remanent polarization, given data can be stored in a non-volatile manner. Moreover, by simply applying or removing a positive or negative electric field, it can be ensured that the polarization state of the ferroelectric material of the above-mentioned capacitor element shifts only between points B and C or between points D and E, instead of having polarization inversions. Thus, given data can be stored in a volatile manner, as in the case of a usual DRAM. However, in order to retain the data thus stored in a volatile manner, a refreshing operation is required as in the case of a DRAM.
A ferroelectric type NVDRAM has the advantage that, since the memory cells thereof can be constituted by a smaller number of elements than in the case of a DRAM/EEPROM type NVDRAM, the cell areas can be reduced, thereby providing for further integration of the device. On the other hand, a DRAM/EEPROM type NVDRAM has the advantage that different data can be stored in the DRAM and the EEPROM included in the NVDRAM.
The structure and operation of a DRAM/EEPROM type NVDRAM are well known, and descriptions thereof can be found in the above-mentioned literatures. Hereinafter, the structure and operation of an exemplary ferroelectric type NVDRAM, where a two transistor/cell method is used, will be described. The two transistor/cell method is known to be immune to possible variations in the fabrication process.
As shown in FIG. 2, this ferroelectric type NVDRAM includes a plurality of word lines WL and corresponding plate lines PL. The word lines WL are connected to a word line decoder 31. The plate lines PL are connected to a plate line decoder 32. The NVDRAM also includes a plurality of pairs of bit lines bit and bit. Each pair of bit lines bit and bit are connected to a sense amplifier 33. In FIG. 2, only one pair of bit lines bit and bit and their corresponding sense amplifier 33 are shown.
A memory cell 34 is provided in each portion where one of the word lines WL and its corresponding plate line PL intersect a pair of bit lines bit and bit. In FIG. 2, only one memory cell 34 is shown. The memory cell 34 includes two capacitor elements C.sub.1 and C.sub.2 and two selection transistors Q.sub.1 and Q.sub.2. One of the terminals of the capacitor element C.sub.1 is connected to the bit line bit via the transistor Q.sub.1. One of the terminals of the capacitor element C.sub.2 is connected to the bit line bit via the transistor Q.sub.2. The other terminals of the capacitor elements C.sub.1 and C.sub.2 are connected to the plate line PL. Gates of the transistors Q.sub.1 and Q.sub.2 are connected to the word line WL.
The above-described ferroelectric type NVDRAM operates in the following manner. The word line decoder 31 and the plate line decoder 32 select, respectively, one of the word lines WL and one of the plate lines PL, in accordance with an address signal input to an address buffer 35. Then, the memory cell 34 is accessed in a mode chosen in accordance with a control signal input to a control signal input buffer 36. Specifically, the access operation is conducted in one of the following modes: in a DRAM-mode for accessing data to be stored in a volatile manner, the NVDRAM is controlled by a DRAM-mode timing control circuit 37; in a recall-mode for reading and rewriting data stored in a non-volatile manner, the NVDRAM is controlled by a recall-mode timing control circuit 38; in a store-mode for writing data to be stored in a non-volatile manner, the NVDRAM is controlled by a store-mode timing control circuit 39. The inputting and the outputting of the data to be accessed are conducted through a data I/O interface 40.
Hereinafter, a writing operation of data in the store-mode, controlled by the store-mode timing control circuit 39, will be described with reference to FIGS. 3 and 4.
As shown in FIG. 3, when data "0" is to be written, for example, a voltage of 0 V and a voltage of 5 V (i.e. supply voltage Vcc) are applied to, respectively, the bit line bit and the bit line bit, and a voltage pulse which varies from 0 V to 5 V and back to 0 V is applied to the plate line PL while keeping the word line WL in an active state. As a result, the polarization state of the ferroelectric material of the capacitor element C.sub.1 shifts from point C or point E to point B, and then to point C as shown in FIG. 1. The polarization state of the ferroelectric material of the capacitor element C.sub.2 shifts from point D to point E and back to point D as shown in FIG. 1. Accordingly, after these voltages are stopped being applied, the ferroelectric materials of the capacitor elements C.sub.1 and C.sub.2 have the remanent polarizations of points C and E, respectively, so that the data "0" is stored in a non-volatile manner.
When data "1" is to be written, as shown in FIG. 4, a voltage of 5 V (i.e. supply voltage Vcc) and a voltage of 0 V are applied to, respectively, the bit line bit and the bit line bit, in contrast to the voltages of 0 V and 5 V applied in the above-mentioned case of writing the data "0". A voltage pulse which varies from 0 V to 5 V and back to 0 V is applied to the plate line PL while keeping the word line WL in an active state, whereby the ferroelectric materials of the capacitor elements C.sub.1 and C.sub.2 are made to have the remanent polarizations of points E and C, respectively, so that the data "1" is stored in a non-volatile manner.
Next, a recalling operation of data in the recall-mode, controlled by the recall-mode timing control circuit 38, will be described with reference to FIG. 5. In this operation, the pair of bit lines bit and bit are precharged at a voltage of 0 V and thereafter are placed in an open state. Then, a voltage which varies from 0 V to 5 V is applied to the plate line PL while keeping the word line WL in an active state. As a result, in the case where data "0" is stored, the polarization state of the ferroelectric material of the capacitor element C.sub.1 shifts from point C to point B as shown in FIG. 1, while the polarization state of the ferroelectric material of the capacitor element C.sub.2 shifts from point E to point B. Thus, the polarization state of the ferroelectric material of the capacitor element C.sub.2 is inverted, so that the potential of the bit line bit, which is connected to the capacitor element C.sub.2, becomes higher than that of the bit line bit by several hundred mV (millivolts). Accordingly, by sensing the difference between the potentials of the bit lines bit and bit by the sense amplifier 33, the data stored in a non-volatile manner can be read out. However, the polarization states of the capacitor elements C.sub.1 and C.sub.2 both shift to point B, so that the data which has been stored in a non-volatile manner is lost, resulting in a destructive read-out of the data.
In the recall-mode, the data which has been recalled can be rewritten in the NVDRAM by storing the data in a non-volatile manner. This can be conducted by, after the pair of bit lines bit and bit are set at 0 V and 5 V by the sense amplifier 33, applying a voltage which varies from 0 V to 5 V and back to 0 V to the plate line PL in the same procedure as that for the store-mode. In addition, by maintaining the plate line PL at 0 V after the above procedure, the potentials set for the pair of bit lines bit and bit can be stored in the memory cell 34 as charges, thus realizing storage in a DRAM mode (to be described later).
The potential difference in the pair of bit lines bit and bit which is generated in the recall-mode is in proportion to the intensity of the remanent polarization and in inverse proportion to the bit line capacitance. Accordingly, a larger potential difference can be obtained as the remanent polarization increases and as the bit line capacity decreases, thereby facilitating the detection by the sense amplifier 33.
An accessing operation in the DRAM-mode, controlled by the DRAM-mode timing control circuit 37, is achieved by the same procedure as that for a conventional DRAM except that a voltage of 0 V or 5 V (i.e. supply voltage Vcc) is applied to the plate line PL. Thus, the polarization states of the ferroelectric materials of the capacitor element C.sub.1 and C.sub.2 shift only between point D and point E or between point B and point C, neither of which results in any inversion of polarization. Therefore, the reading and writing of the data stored in a volatile manner can be conducted by utilizing the charges stored in the capacitor element C.sub.1 and C.sub.2 alone, as in the case of a conventional DRAM. In addition, a refreshing operation can be conducted.
Although a ferroelectric type NVDRAM of a two transistor/cell type, which is relatively immune to influences of the fluctuation in the thickness of the ferroelectric material film, was described above, substantially the same principle applies to an NVDRAM having a memory cell array structure of one transistor/cell type having relatively small cell areas and thus being suitable for higher degrees of integration, such as that disclosed in Japanese Patent Application No. 4-324506.
It is possible to operate either of the DRAM/EEPROM type NVDRAM and the ferroelectric type NVDRAM described above exclusively in the store-mode for storing data in a non-volatile manner and in the recall-mode for recalling the stored data.
However, in the case of a DRAM/EEPROM type NVDRAM, the EEPROM does not permit rewriting that exceeds one hundred thousand times or more, so that the EEPROM will soon reach the end of its lifetime if frequent rewriting operations are conducted.
In the case of a ferroelectric type NVDRAM, the ferroelectric materials included in the capacitor elements C.sub.1 and C.sub.2 permits only a limited number of polarization inversions, so that the recalling/storing operations are limited to about 10.sup.8 to 10.sup.12 times. Therefore, the lifetime of the memory cells 34 can expire in a few days by conducting successive accessing at a cycle period of about 10 MHz. Therefore, studies are conducted on materials which leave a large remanent polarization and permit a large number of polarization inversions.
In view of the above problems, in the case of a DRAM/EEPROM type NVDRAM, the EEPROM is prevented from undergoing an excessively large number of rewriting operations by ensuring that only the DRAM is accessed during usual operations, so that the data stored in the DRAM is saved in the EEPROM only immediately before the NVDRAM is turned off, and that the data is recalled into the DRAM in a recall-mode when the NVDRAM is turned on the next time. In the case of a ferroelectric type NVDRAM, the number of the accessing operations that result in polarization inversions is minimized by ensuring that accessing operations in the DRAM-mode, which do not result in any inversion of polarization, are conducted during usual operations and that the data in the memory cells 34 is stored in a non-volatile manner only before the NVDRAM is turned off, the stored data only being recalled in the recall-mode in the first reading operation when the NVDRAM is turned on the next time.
A conventional NVDRAM performs the above-mentioned recalling operations and refreshing operations in accordance with a combination of a plurality of external input signals. Specifically, a recalling operation is conducted by activating, or setting at the low level, a non-volatile storage enable signal NE, a chip enable signal CE, and an output enable signal OE, and by inactivating, or setting at the high level, a write enable signal WE and a refresh signal RFSH. A refreshing operation for the volatile storage is conducted by activating the chip enable signal CE alone and by supplying an address signal from the outside.
The refreshing operation for the volatile storage can be automatically conducted, without frequently varying the external input signals, by activating the refresh signal RFSH alone so that a self-refreshing is achieved with the use of an internal counter, as in the case of a pseudo SRAM (Static RAM). It is also applicable to so configurate the NVDRAM that the output enable signal OE also functions as the refresh signal RFSH in order to reduce the number of pins on the NVDRAM. However, even in the case of conducting such self-refreshing, it is necessary to previously recall the data stored in a non-volatile manner, in a recalling operation, so as to conduct a volatile storage for the recalled data.
Therefore, a conventional NVDRAM requires a recalling operation before an accessing operation in the DRAM-mode, thereby necessitating controlling of a combination of the external input signals. This results in the problem that a more complex control is required than in the case of other memory devices such as pseudo SRAMs. This problem is also common to the case where the NVDRAM is constructed by using SRAMs, which do not require refreshing operations.
Moreover, during a refreshing operation in the DRAM-mode, a relatively large current of about 200 .mu.A is required. This has led to the strong demand for the reduction in the power consumption of NVDRAMs, whose applications as in IC cards and memory devices in portable electric equipments are attracting much attention. However, there is a limit to the reduction in the power consumption of NVDRAMs during the refreshing operations by elaborating the internal circuitry thereof or by improving the fabrication process for the semiconductor material used therein. The power consumption can also be reduced by applying strict limitations in terms of margin values to the specification of the data retaining current, that is, by reducing the margin areas. However, this results in another problem in that the yield of the NVDRAMs may decrease.
The above-mentioned problems are common to both the case where the NVDRAM is realized as a separate memory device and the case where the memory cell is realized as a memory module for a single chip microcomputer.